Field of the Invention
The present invention relates to electronic chip packaging and to methods of manufacturing of same.
Description of the Related Art
Consumer electronics such as computing and telecommunication devices include integrated circuit chips.
The classical approach for enabling the coupling of chips to the outside world is to include an IC substrate as part of the chip packaging. The packaged chip has connections such as a ball grid array BGA or a land grid array LGA for coupling to a printed circuit board PCB or other substrate to which other components are coupled.
The IC substrate is required to have high planarity and to be stiff and warp resistant to ensure good contact with PCBs and other underlying substrates. The general requirement for IC substrates in particular and for chip packaging in general is reliability and appropriate electrical performance, thinness, stiffness, planarity, good heat dissipation and a competitive unit price.
A well established common type of chip package that is comparatively cheap and enables IC circuits to communicate with the outside world is the lead frame. The lead frame uses metal leads that extend outside the housing. Lead frame technology goes back to the early days of DIP chips, but is still widely used in many package varieties.
The lead frame serves as the ‘skeleton’ of the IC package, providing mechanical support to the die during its assembly into a finished product. It consists of a die paddle, to which the die is attached, and leads, which serve as the means for external electrical connection to the outside world. The die is connected to the leads by wires through wire bonding or by tape automated bonds.
Once attached to the lead frame with the connecting wires, the die or chip is covered with a plastic protective material that is known as a molding compound.
Technologies that are used for fabricating more advanced multilayer substrates comprise layers of connecting pads or features embedded within dielectric material. Vias are provided through the dielectric material to electronically couple together features in different layers.
One method for fabricating such vias is by drill & fill, wherein holes are drilled through the dielectric, typically using a laser, and a conductive material, such as copper is used to fill the hole, creating a via.
An alternative approach to fabricate vias is by depositing copper or other metal into a pattern created in a photo-resist by selective exposure to light of an appropriate wavelength, typically ultraviolet, either by selective exposure to a lamp through a stencil or by writing the pattern using a laser scribe. This technology of electroplating into a pattern developed into a photo-resist is known as ‘pattern plating’. The photo-resist is subsequently removed and the upstanding via posts are laminated with a dielectric material that is preferably a polymer impregnated glass fiber mat pre-preg for enhanced stiffness.
In pattern plating, a seed layer is first deposited. Then a layer of photo-resist is deposited thereover and subsequently exposed to create a pattern which is selectively removed to make trenches that expose the seed layer. Via posts are created by depositing copper into the trenches in the photo-resist. The remaining photo-resist is then removed, the seed layer is etched away, and a dielectric material that is, again, typically a polymer impregnated glass fiber mat prepreg, is laminated thereover and therearound to encase the vias posts. Various techniques and processes can be then use to thin down the dielectric material, planarizing it and exposing the tops of the via posts allowing conductive connection to a ground or reference plane thereby, for building up the next metal layer thereupon. Subsequent layers of metal conductors and via posts may be deposited thereonto, by repeating the process to build up a desired multilayer structure.
In an alternative but closely linked technology, known hereinafter as ‘panel plating’, a continuous layer of metal or alloy is deposited onto a substrate. A layer of photo-resist is deposited on top of this and a pattern is developed within the photo-resist. Subsequently the developed photo-resist is selectively stripped away, selectively exposing the metal thereunder, which may then be etched away. The undeveloped photo-resist protects the underlying metal from being etched away, and leaves a pattern of upstanding features and vias. After stripping away the undeveloped photo-resist, a dielectric material, such as a polymer impregnated glass fiber mat, may be laminated around and over the upstanding copper features and/or via posts. In yet other variants, a pattern of undeveloped photoresist is stripped away leaving the developed photoresist to act as a mask.
The via layers created by pattern plating or panel plating methodologies such as those described above, are typically known as ‘via posts’. Feature layers may be fabricated using similar techniques.
One flexible technology for fabricating high density interconnects is to build up pattern or panel plated multilayer structures consisting of metal vias or features in a dielectric matrix. The metal used for the vias and features may be copper, and the dielectric may consist of a fiber reinforced polymer matrix. Typically, a polymer with a high glass transition temperature (Tg) is used, such as polyimide, for example. These interconnects may be cored or coreless, and may include cavities for stacking components. They may have odd or even numbers of layers. Enabling technology is described in previous patents issued to Amitec-Advanced Multilayer Interconnect Technologies Ltd. For example, U.S. Pat. No. 7,682,972 to Hurwitz et al. titled “Advanced Multilayer Coreless Support Structures and Method for their Fabrication” describes a method of fabricating a free standing membrane including a via array in a dielectric, for use as a precursor in the construction of superior electronic support structures. The method includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing the laminated array, followed by terminating the vias. This publication is incorporated herein by reference in its entirety.
U.S. Pat. No. 7,635,641 to Hurwitz et al. titled “Integrated Circuit Support Structures and their Fabrication” describes a method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (E) applying a protective coating of photo-resist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photo-resist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto. This publication is incorporated herein by reference in its entirety.
Multilayer substrates enable a higher density of connections and are used with ever more sophisticated IC chips. They are more expensive than simple single layer lead frames, and for many electronic applications, the more economical lead frame is suitable.
Even for packaging relatively simple chips where a single layer is adequate, lead frame technology has its limitations. The chip is attached to the lead frame by wire bonding and the longer the connecting wires, the greater the danger of a wire breaking, creating a disconnect and leading to failure. Additionally, the closer the wires are packed together, the greater the likelihood of shorting.
The via post in dielectric material approach is suitable for multilayer substrates but is generally too flimsy to be used in single layer structures, since it will be appreciated that warping and bending create poor contacts, unreliability and shorting.
U.S. Pat. No. 8,866,286 to Hurwitz et al. titled “Single Layer Coreless Substrate” describes an electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer, wherein the via post layer is surrounded by a dielectric material comprising glass fibers in a polymer resin, and the chip and routing layer are embedded in a second layer of dielectric material encapsulating the chip and the routing layers. In this packaging technology, the copper ends of the via posts are flush with the dielectric material.
The package is fairly robust but may be subject to over-heating. Additionally, such packages may have stray inductances due to the wire bonds and may be costly to manufacture due to the assembly processes and materials required for the die-attachment, the wire-bonding and molding.
Co-pending application number U.S. Ser. No. 14/789,165 describes an embedded die package comprising a die having die contact pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesion/barrier layer, pillars extending from a second side of the feature layer, the die, feature layer and pillars being encapsulated by a dielectric material.
Also described therein, is a method for fabricating such structures consisting of:
Obtaining a grid of sockets surrounded by a polymer frame;
Placing the grid of chip sockets on a tape;
Placing chips face down (flip chip) in the sockets of the grid;
Laminating a dielectric material over the dies and the grid;
Applying a carrier over the dielectric;
Depositing an adhesive layer comprising at least one of titanium, tantalum, tungsten, chrome and/or nickel followed by a seed layer of copper onto newly exposed surface;
Applying a layer of first layer of photoresist and develop a pattern with a feature layer.
Electroplating copper into the pattern to form features;
Stripping away the first layer of photoresist;
Applying a second layer of photoresist patterned with a pattern of via pillars;
Electroplating copper into the pattern to form via pillars;
Stripping away the second layer of photoresist;
Etching away exposed portions of the adhesive layer and the copper seed layer;
Applying a dielectric barrier layer covering the copper features, pillars and undersides of the chips;
Removing carrier;
Laminating a thin layer of black dielectric over the back of the array of dies;
Thinning the dielectric to expose the copper pillars;
Applying terminations, and
Dicing the grid into individual packaged chips.
The method is a build up method. The routing tracks of the feature layer are deposited over the pads of the embedded chip and after lamination of these routing tracks, the pads are created as a further layer which is then laminated the pads are then terminated as a Land Grid Array or as a Ball Grid Array.
In consequence of the layered manufacturing technique of this packaging technique as previously disclosed, there is a problem of alignment that may reduce yields and thus increase unit cost, or, to enable high yields despite the alignment issue, may limit the applicability of the technique to the packaging relatively simple and large dies with few terminations. Where an array of dies is processed simultaneously, each die is positioned in its socket and, after lamination; a feature layer consisting of routing lines is applied to the entire array. The sockets have to be larger than the dice, i.e. clearance is required for positioning the dice. Typically, the manufacturing tolerance is ±10 microns for the socket if it is formed by dissolution of sacrificial copper, and ±5 microns for the dice which are cut from a wafer, and the cutting technology, whether laser or blade, has its inherent variations. In addition to the manufacturing tolerances of the die dimensions and the manufacturing tolerances of the sockets, for picking and placing the dice into the sockets a clearance is required. Consequently, the individual sockets have to be a minimum of 15 microns larger than the die in each direction to ensure that the die will be smaller than the socket, and in consequence, may be 30 microns smaller. This means that the actual positions of the die I/O contacts may be shifted towards one edge or another of the sockets over a distance of 30 microns. Additionally, the individual dice may be rotated slightly with respect to their sockets.
The dice have to be individually picked up and placed into the socket and the pick and place robots have their positioning accuracy limitations as well and it seems that the current state of the art is tolerances of ±50 microns.
If the array of chip packages is processed by developing patterns of routing lines in photoresist using a mask, the routing lines may be accurately aligned with the chip sockets (although even this alignment may be ±10 microns), but won't be optimally aligned with the I/O pillars of the individual dice which could be shifted by as much as 50 microns. This can adversely affect reliability of the contacts between the dice input output pads and the routing lines, and/or yields and thus unit cost.
One way of overcome these limitations, is to limit usage of the technology to relatively simple chips with few outlets allowing routing traces with large ends chip ends for reliably engaging the chip I/O pillars, regardless of the shift or rotation of the chips within their sockets prior to their being fixed by a dielectric filler. It will be appreciated however, that, as illustrated by Moore's Law, the microelectronics industry strives for ever greater complexity, reduction in sizes and increases in cost and reliability.
For the embedded packaging technique of U.S. Ser. No. 14/789,165 and similar embedded technologies to enable reliable, cheap packaging of ever-more complicated IC chips it is necessary to overcome this barrier. Embodiments of the present invention address this issue.